W968D6DA Datasheet, PDF (40/75 Pages) Winbond – Low-power features

W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
10. TIMING REQUIRMENTS
10.1 Read, Write Timing Requirements
10.1.1 Asynchronous READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Parameter
Symbol Min Max Unit Note
Address access time
tAA
-
70
ns
ADV# access time
tAADV
-
70
ns
Page access time
tAPA
-
20
ns
Address hold from ADV# HIGH
tAVH
2
-
ns
Address setup to ADV# HIGH
tAVS
5
-
ns
LB#/UB# access time
tBA
-
70
ns
LB#/UB# disable to DQ High-Z Output
tBHZ
-
8
ns
1
LB#/UB# enable to Low-Z output
tBLZ
6
-
ns
2
Maximum CE# pulse width
tCEM
-
4
μs
3
CE# LOW to WAIT valid
tCEW
1 7.5
ns
Chip select access time
tCO
-
70
ns
CE# LOW to ADV# HIGH
tCVS
7
-
ns
Chip disable to DQ and WAIT High-Z output
tHZ
-
8
ns
1
Chip enable to Low-Z output
tLZ
6
-
ns
2
Output enable to valid output
tOE
-
20
ns
Output hold from address change
tOH
5
-
ns
Output disable to DQ High-Z output
tOHZ
-
8
ns
1
Output enable to Low-Z output
tOLZ
3
-
ns
2
Page READ cycle time
tPC
20
-
ns
READ cycle time
tRC
70
-
ns
ADV# pulse width LOW
tVP
5
-
ns
Note: 1.Low-Z to High-Z timings are tested with AC Output Load Circuit. The High-Z timings measure a 100mV transition from
either VOH or VOL toward VCCQ/2.
2. High-Z to Low-Z timings are tested with AC Output Load Circuit. The Low-Z timings measure a 100mV transition away
from the High-Z (VCCQ/2) level toward either VOH or VOL.
3. Applies to all modes.
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Publication Release Date : June 27, 2013
Revision : A01-003