W968D6DA Datasheet, PDF (17/75 Pages) Winbond – Low-power features

W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
8.2.4 Mixed-Mode Operation
The device supports a combination of synchronous READ and asynchronous READ and asynchronous WRITE E
operations when the BCR is configured for synchronous operation. The asynchronous READ and asynchronous
WRITE operations require that the clock (CLK) remain LOW during the entire sequence. The ADV# signal can be
used to latch the target address, or it can remain LOW during the entire asynchronous WRITE operation. CE# can
remain LOW when transitioning between mixed-mode operations with fixed latency enabled; however, the CE# LOW
time must not exceed tCEM. Mixed-mode operation facilitates a seamless interface to legacy burst mode flash
memory controllers.
8.2.4.1 WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, system level WAIT signal. The shared
WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus.
8.2.4.2 Wired-OR WAIT Configuration
READY
Processor
CellularRAM
WAIT
WAIT
Other
Device
WAIT
Other
Device
External
Pull - Up/ Pull - Down
Resistor
Once a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device
requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid
data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be
accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on
successive clock edges.
CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT configuration BCR[8] = 1). Bringing CE#
HIGH during WAIT cycles may cause data corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one
cycle after WAIT de-asserts, and at the end of the row the WAIT cycles start one cycle after the WAIT signal
asserts.)
When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for READ
operations launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional
clock cycles until the refresh has completed. When the refresh operation has completed, the READ operation will
continue normally.
WAIT will be asserted but should be ignored during asynchronous READ and WRITE, and page READ operations.
By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst mode without monitoring
the WAIT signal. However, WAIT can still be used to determine when valid data is available at the start of the burst
and at the end of the row. If WAIT is not monitored, the controller must stop burst accesses at row boundaries on its
own.
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Publication Release Date : June 27, 2013
Revision : A01-003