W968D6DA Datasheet, PDF (23/75 Pages) Winbond – Low-power features

W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
8.4.1.5 Register READ, Synchronous Mode Followed by READ ARRAY Operation
CLK
A [ max : 0 ]
( except A [ 19 : 18 ] )
A [ 19 : 18 ] ²
CRE
ADV #
CE #
Latch Control Register Value
tSP
Latch Control Register Address
tSP
tHD
tSP
tHD
Address
Address
tHD _tABA
tCSP
tCBPH *³
tHZ
OE #
WE #
tSP
LB # / UB #
tCW
High - Z
WAIT
DQ [ 15:0 ]
tOHZ
tBOE
tHD
tOLZ tACLK
CR Valid
tKOH
High - Z
Don‟t Care
Data
Valid
Undefined
Note : 1. Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code 2
(3 clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19:18] = 00b to read RCR, 10b to read BCR , and 01b to read DIDR.
3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored – additional WAIT cycles caused
by refresh collisions require a corresponding number of additional CE# LOW cycles.
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Publication Release Date : June 27, 2013
Revision : A01-003