W968D6DA Datasheet, PDF (3/75 Pages) Winbond – Low-power features

W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ........................................................................................................ 1
2. FEATURES................................................................................................................................ 1
3. ORDERING INFORMATION ..................................................................................................... 2
4. PIN CONFIGURATION.............................................................................................................. 6
4.1 Ball Assignment ................................................................................................................................... 6
5. PIN DESCRIPTION ................................................................................................................... 7
5.1 Signal Description ................................................................................................................................ 7
6. BLOCK DIAGRAM .................................................................................................................... 8
6.1 Block Diagram......................................................................................................................................8
6.2 CellularRAM - Interface Configuration Options .................................................................................... 9
7. INSTRUCTION SET ................................................................................................................ 10
7.1 Bus Operation .................................................................................................................................... 10
8. FUNCTIONAL DESCRIPTION ................................................................................................ 11
8.1 Power Up Initialization ....................................................................................................................... 11
8.1.1 Power-Up Initialization Timing ...................................................................................................................... 11
8.2 Bus Operating Modes ........................................................................................................................ 11
8.2.1 Asynchronous Modes ................................................................................................................................... 11
8.2.1.1 READ Operation(ADV# LOW)................................................................................................................................. 12
8.2.1.2 WRITE Operation (ADV# LOW) .............................................................................................................................. 12
8.2.2 Page Mode READ Operation........................................................................................................................ 13
8.2.2.1 Page Mode READ Operation (ADV# LOW) ............................................................................................................ 13
8.2.3 BURST Mode Operation ............................................................................................................................... 13
8.2.3.1 Burst Mode READ (4-word burst)............................................................................................................................ 14
8.2.3.2 Burst Mode WRITE (4-word burst) .......................................................................................................................... 15
8.2.3.3 Refresh Collision During Variable-Latency READ Operation .................................................................................. 16
8.2.4 Mixed-Mode Operation ................................................................................................................................. 17
8.2.4.1 WAIT Operation ...................................................................................................................................................... 17
8.2.4.2 Wired-OR WAIT Configuration ................................................................................................................................ 17
8.2.5 LB#/ UB# Operation ...................................................................................................................................... 18
8.3. Low Power Operation ....................................................................................................................... 18
8.3.1 Standby Mode Operation .............................................................................................................................. 18
8.3.2 Temperature Compensated Refresh ............................................................................................................ 18
8.3.3 Partial Array Refresh..................................................................................................................................... 18
8.3.4 Deep Power-Down Operation ....................................................................................................................... 18
8.4 Registers ............................................................................................................................................ 19
8.4.1 Access Using CRE........................................................................................................................................ 19
8.4.1.1 Configuration Register WRITE, Asynchronous Mode Followed by READ ARRAY Operation ................................ 19
8.4.1.2 Configuration Register WRITE – CE# control ......................................................................................................... 20
8.4.1.3 Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation .................................. 21
8.4.1.4 Register READ, Asynchronous Mode Followed by READ ARRAY Operation ........................................................ 22
8.4.1.5 Register READ, Synchronous Mode Followed by READ ARRAY Operation .......................................................... 23
8.4.2 Software Access ........................................................................................................................................... 24
8.4.2.1 Load Configuration Register.................................................................................................................................... 24
8.4.2.2 Read Configuration Register ................................................................................................................................... 25
8.4.3 Bus Configuration Register ........................................................................................................................... 25
8.4.3.1 Bus Configuration Register Definition ..................................................................................................................... 26
8.4.3.2 Burst Length (BCR[2:0]) Default = Continuous Burst .............................................................................................. 27
8.4.3.3 Burst Wrap (BCR[3]) Default = No Wrap ................................................................................................................. 27
8.4.3.4 Sequence and Burst Length.................................................................................................................................... 28
8.4.3.5 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength.................................................................... 29
8.4.3.6 Table of Drive Length .............................................................................................................................................. 29
8.4.3.7 WAIT Signal in Synchronous Burst Mode............................................................................................................. 29
8.4.3.8 WAIT Config. (BCR[8]) Default = 1 Clk Before Data Valid/Invalid ........................................................................... 29
8.4.3.9 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH ........................................................................................... 29
Publication Release Date : June 27, 2013
-3-
Revision : A01-003