W25N01GVZEIT-TR Datasheet, PDF (48/68 Pages) Winbond – 3V 1G-BIT SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ

W25N01GVxxIG/IT
8.2.23 Fast Read Dual I/O with 4-Byte Address (BCh)
The Fast Read Dual I/O (BCh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Column Address or the dummy clocks two bits per clock. This reduced instruction overhead may allow
for code execution (XIP) directly from the Dual SPI in some applications.
The Fast Read Quad Output instruction sequence is shown in Figure 27a & 27b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be following
and continues through the entire memory array. This allows using a single Read instruction to read out the
entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
Figure 27a. Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
CLK
Mode 3
Mode 0
DI
(IO0)
0
789
19 20 21
Instruction
BCh
38 36 34
20 Dummy Clocks
16 14 12
DO
(IO1)
High Impedance
39 37 35
17 15 13
27 28 29 30 31 32 33 34 35 36
0642064206
Data Out 1
Data Out 2
1753175317
* _{* = MSB}
*
*
Figure 27b. Fast Read Dual I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
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