W25N01GVZEIT-TR Datasheet, PDF (17/68 Pages) Winbond – 3V 1G-BIT SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ

W25N01GVxxIG/IT
7.1.2 Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable
The Write Protection Enable bit (WP-E) is a volatile read/write bits in the status register-1 (S1). The WP-E
bit, in conjunction with SRP1 & SRP0, controls the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection, /WP pin functionality, and
Quad SPI operation enable/disable. When WP-E = 0 (default value), the device is in Software Protection
mode, /WP & /HOLD pins are multiplexed as IO pins, and Quad program/read functions are enabled all the
time. When WP-E is set to 1, the device is in Hardware Protection mode, all Quad functions are disabled
and /WP & /HOLD pins become dedicated control input pins.
7.1.3 Status Register Protect Bits (SRP1, SRP0) – Volatile Writable, OTP lockable
The Status Register Protect bits (SRP1 and SRP0) are volatile read/write bits in the status register (S0 and
S7). The SRP bits control the method of write protection: software protection, hardware protection, power
supply lock-down or one time programmable (OTP) protection.
Software Protection (Driven by Controller, Quad Program/Read is enabled)
SRP1 SRP0 WP-E /WP / IO2
0
0
0
X
0
1
0
0
0
1
0
1
1
0
0
X
1
1
0
X
Descriptions
No /WP functionality
/WP pin will always function as IO2
SR-1 cannot be changed (/WP = 0 during Write Status)
/WP pin will function as IO2 for Quad operations
SR-1 can be changed (/WP = 1 during Write Status)
/WP pin will function as IO2 for Quad operations
Power Lock Down⁽¹⁾ SR-1
/WP pin will always function as IO2
Enter OTP mode to protect SR-1 (allow SR1-L=1)
/WP pin will always function as IO2
Hardware Protection (System Circuit / PCB layout, Quad Program/Read is disabled)
SRP1 SRP0 WP-E /WP only
Descriptions
0
X
1
VCC
SR-1 can be changed
1
0
1
VCC
Power Lock-Down⁽¹⁾ SR-1
1
1
1
VCC
X
X
1
GND
Enter OTP mode to protect SR-1 (allow SR1-L=1)
All "Write/Program/Erase" commands are blocked
Entire device (SRs, Array, OTP area) is read-only
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
- 16 -
Publication Release Date: March 21, 2016
Revision G