W25N01GVZEIT-TR Datasheet, PDF (13/68 Pages) Winbond – 3V 1G-BIT SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ

6. FUNCTIONAL DESCRIPTIONS
6.1 Device Operation Flow
W25N01GVxxIG/IT
Power Up
(default BUF=1, ECC-E=1)
Initialization &
Default Page Load (00) ~500us
Power Up
(default BUF=0, ECC-E=1)
Initialization &
Default Page Load (00) ~500us
Read
page 00?
Y
N
Load Page xx
tRD ~50us
Read
page 00?
Y
N
Load Page xx
tRD ~50us
Start “Buffer Read” with column address
(Page 00 or Page xx)
Start “Continuous Read” from column 0
(Page 00 or Page xx)
Set BUF=0
Set BUF=1
Load Page yy
tRD ~50us
Load Page yy
tRD ~50us
Start “Continuous Read” from column 0
(Page yy)
Start “Buffer Read” with column address
(Page yy)
W25N01GVxxIG
W25N01GVxxIT
Figure 3. W25N01GV Flash Memory Operation Diagram
6.1.1 Standard SPI Instructions
The W25N01GV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI
input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO
output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising
edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
6.1.2 Dual SPI Instructions
The W25N01GV supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical
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Publication Release Date: March 21, 2016
Revision G