W25N01GVZEIT-TR Datasheet, PDF (31/68 Pages) Winbond – 3V 1G-BIT SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ

W25N01GVxxIG/IT
8.2.5 Write Enable (06h)
The Write Enable instruction (Figure 9) sets the Write Enable Latch (WEL) bit in the Status Register to a 1.
The WEL bit must be set prior to every Page Program, Quad Page Program and Block Erase instruction.
The Write Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data
Input (DI) pin on the rising edge of CLK, and then driving /CS high.
Figure 9. Write Enable Instruction
8.2.6 Write Disable (04h)
The Write Disable instruction (Figure 10) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Page Program, Quad Page Program, Block Erase and Reset instructions.
Figure 10. Write Disable Instruction
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Publication Release Date: March 21, 2016
Revision G