W25N01GVZEIT-TR Datasheet, PDF (35/68 Pages) Winbond – 3V 1G-BIT SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ

W25N01GVxxIG/IT
8.2.10 128KB Block Erase (D8h)
The 128KB Block Erase instruction sets all memory within a specified block (64-Pages, 128K-Bytes) to the
erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the
Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the
/CS pin low and shifting the instruction code “D8h” followed by 8-bit dummy clocks and the 16-bit page
address. The Block Erase instruction sequence is shown in Figure 14.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if
the addressed block is protected by the Block Protect (TB, BP2, BP1, and BP0) bits.
Figure 14. 128KB Block Erase Instruction
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Publication Release Date: March 21, 2016
Revision G