W25N01GVZEIT-TR Datasheet, PDF (15/68 Pages) Winbond – 3V 1G-BIT SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ

W25N01GVxxIG/IT
6.2 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25N01GV
provides several means to protect the data from inadvertent writes.
• Device resets when VCC is below threshold
• Write enable/disable instructions and automatic write disable after erase or program
• Software and Hardware (/WP pin) write protection using Protection Register (SR-1)
• Lock Down write protection for Protection Register (SR-1) until the next power-up
• One Time Program (OTP) write protection for memory array using Protection Register (SR-1)
• Hardware write protection using /WP pin when WP-E is set to 1
Upon power-up or at power-down, the W25N01GV will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 30a). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Program Execute, Block Erase and the Write Status Register instructions. Note
that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL
time delay is reached, and it must also track the VCC supply level at power-down to prevent adverse
command sequence. If needed a pull-up resister on /CS can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Program Execute or
Block Erase instruction will be accepted. After completing a program or erase instruction the Write Enable
Latch (WEL) is automatically cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP0, SRP1) and Block Protect (TB, BP[3:0]) bits. These settings allow a portion
or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP)
pin, changes to the Status Register can be enabled or disabled under hardware control. See Protection
Register section for further information.
The WP-E bit in Protection Register (SR-1) is used to enable the hardware protection. When WP-E is set
to 1, bringing /WP low in the system will block any Write/Program/Erase command to the W25N01GV, the
device will become read-only. The Quad SPI operations are also disabled when WP-E is set to 1.
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Publication Release Date: March 21, 2016
Revision G