W25N01GVZEIT-TR Datasheet, PDF (29/68 Pages) Winbond – 3V 1G-BIT SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ

W25N01GVxxIG/IT
8.2.3 Read Status Register (0Fh / 05h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered
by driving /CS low and shifting the instruction code “0Fh or 05h” into the DI pin on the rising edge of CLK
followed by an 8-bit Status Register Address. The status register bits are then shifted out on the DO pin at
the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7. Refer to section 7.1-3 for
Status Register descriptions.
The Read Status Register instruction may be used at any time, even while a Program or Erase cycle is in
progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the
device can accept another instruction. The Status Register can be read continuously. The instruction is
completed by driving /CS high.
Figure 7. Read Status Register Instruction
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Publication Release Date: March 21, 2016
Revision G