TI380PCI Datasheet, PDF (9/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

PIN
NAME
NO.
AD31
27
AD30
29
AD29
30
AD28
32
AD27
33
AD26
35
AD25
36
AD24
38
AD23
42
AD22
43
AD21
44
AD20
45
AD19
47
AD18
48
AD17
49
AD16
51
AD15
66
AD14
68
AD13
69
AD12
71
AD11
72
AD10
73
AD09
74
AD08
75
AD07
78
AD06
80
AD05
81
AD04
83
AD03
84
AD02
85
AD01
86
AD00
87
C/BE3
39
C/BE2
53
C/BE1
65
C/BE0
77
DEVSEL
59
FRAME
55
GNT
25
IDSEL
41
INTA
20
† _{I = in, O = out}
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
Pin Functions – PCI Interface
SPWS020 – AUGUST 1995
I/O†
DESCRIPTION
PCI address and data. A bus transaction to or from one of these pins consists of an address phase
followed by one or more data phases.
The address phase is the clock cycle in which FRAME is asserted. During the address phase
I /O
AD31 – AD00 contain a physical address (32 bits). For I / O, this is a byte address; for configuration and
memory it is a DWORD address. During data phases, AD07– AD00 contain the LSB, and AD31 – AD24
contain the MSB. Write data is stable and valid when IRDY is asserted, and read data is stable and
valid when TRDY is asserted. Data is transferred during those clocks where both IRDY and TRDY are
asserted.
Bus command and byte enables. During the address phase of a transaction, C/BE3 – C/BE0 define the
I /O
bus command. During the data phase, C/BE3 – C/BE0 are used as byte enables. The byte enables are
valid for the entire data phase and they determine which byte lanes carry meaningful data. C/BE0
applies to the LSB and C/BE3 applies to the MSB.
Device select. When DEVSEL is actively driven, it indicates the driving device has decoded its address
I /O
as the target of the current access. As an input, DEVSEL indicates whether any device on the bus has
been selected. If no PCI agent has asserted DEVSEL, then the TI380PCI shall remove itself as the
PCI bus master.
Cycle frame. FRAME is driven by the current master to indicate the beginning and duration of an
I /O
access.
It is asserted to indicate a bus transaction is beginning. While FRAME is asserted, data transfers
continue. When FRAME is deasserted, the transaction is in the final data phase.
I
Grant. GNT indicates to the TI380PCI that access to the PCI bus has been granted. This is a
point-to-point signal.
Initialization device select. IDSEL is used as a chip select during configuration read and write
I
transactions.
O
Interrupt A. INTA is used to request an interrupt. The assertion and deassertion of INTA is asynch-
ronous to PCLK.
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