TI380PCI Datasheet, PDF (22/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
STATUS register—configuration space DWORD address (0x04) (continued)
Bit 12: This bit is set whenever TI380PCI’s transaction is terminated with slave-abort.
Bit 13: This bit is set whenever TI380PCI’s transaction is terminated with master-abort.
Bit 14: This bit is set whenever TI380PCI asserts SERR.
Bit 15: This bit is set by TI380PCI whenever it detects a parity error, even if parity-error handling is disabled
(as controlled by bit 6 in the command register).
board configuration register (Board Config)—configuration space DWORD address (0x44)
31
87
0
0 00 00 00 0 0 0 0 0 0 00 0 0 00 00 00 0
Figure 7. Board Configuration Register
Bits 08 – 31: These bits must read as 0.
Bits 00 – 07: When RST is driven high, the value on ROMA[07:00] is latched into the board configuration register
in the TI380PCI configuration space. The value on ROMA[07:00] can be provided by pullup and pulldown
resistors that do not affect operation after reset. This feature allows designers to support jumpers or
board-stuffing options that can be sensed by software that reads the board configuration register. If pullup and
pulldown registers are not used, the contents of the board configuration register are undefined after reset.
miscellaneous functions
cache line size (CLS)—configuration space DWORD address (0x0c)
The CLS register is loaded with the host system data cache line size. On reset, it is set to 0. The value in this
register controls the TI380PCI FIFO fill / flush algorithm. The value in this register should be a power of two that
is greater than or equal to 4, or a sum of those powers of two.
latency timer (LT)—configuration space DWORD address (0x0C)
The TI380PCI supports burst data transfer on the PCI bus; therefore, a latency timer register is needed as
defined in the PCI specification.
built-in self-test (BIST)—configuration space DWORD address (0x0C)
The TI380PCI does not support built-in self-test and returns 0 when the BIST register is read.
base address register (BASE0)—configuration space DWORD address (0x10)
31
4 3 21 0
Base Address
0 0 00 1
Reserved
I / O Space Indicator
Figure 8. Base Address Register for I / O
The TI380PCI supports only one I / O address range decoded down to eight continuous 32-bit locations. After
reset, the value of the address map is set to 0x1. Bits 0 – 4, are read only as 0x1. The LAN subsystem is expected
to reside in I / O space under normal operations for conformance with the TI2000 software specification.
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