TI380PCI Datasheet, PDF (5/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
Pin Functions – System Interface^†
PIN
NAME
NO.
I/O‡
DESCRIPTION
SADH0 /ROMA08 113
SADH1 /ROMA09 114
SADH2 /ROMA10 115
SADH3 /ROMA11 116
SADH4 /ROMA12 117
SADH5 /ROMA13 119
SADH6 /ROMA14 120
SADH7 /ROMA15 121
System address / data bus — high byte. These lines make up the most significant byte of each
TI380C2x address word (32-bit address bus) and data word (16-bit data bus). The most
significant bit (MSB) is SADH0, and the least significant bit (LSB) is SADH7.
I/O
Address multiplexing bits 31 – 24 and bits 15 – 8§
Data multiplexing bits 15 – 8§
During accesses to the ROM address space from the PCI bus, these lines provide the eight most
significant address bits to the ROM.
SADL0 /ROMD7
132
SADL1 /ROMD6
133
SADL2 /ROMD5
134
SADL3 /ROMD4
135
SADL4 /ROMD3
137
SADL5 /ROMD2
138
SADL6 /ROMD1
139
SADL7 /ROMD0
140
System address / data bus — low byte. These lines make up the least significant byte of each
address word (32-bit address bus) and data word (16-bit data bus). The MSB is SADL0, and the
LSB is SADL7. These address lines also make up the ROM address.
I/O
Address multiplexing bits 23 – 16 and bits 7 – 0§
Data multiplexing bits 7 – 0§
During accesses to the ROM address space from the PCI bus, these lines transfer data from the
ROM to the TI380PCI.
SALE
SBCLK
System address latch enable. SALE is the enable pulse used to externally latch the 16 LSBs of
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the address from the SADH0 – SADH7 and SADL0 – SADL7 buses at the start of the DMA cycle.
Systems that implement address parity also can externally latch the parity bits (SPH and SPL)
for the latched address.
141
O
SIF bus clock. The TI380C2x requires SBCLK to synchronize its bus timings for all DMA transfers
(see Note 1).
SIF bus release. SBRLS indicates to the TI380C2x that a higher-priority device requires the SIF
bus. The value on SBRLS is ignored by the TI380C2x when DMA is not performed.
SBRLS
11
O
H = The TI380C2x can hold onto the system bus.
L = The TI380C2x should release the system bus upon completion of current DMA cycle. If
the DMA transfer is not yet complete, the SIF rearbitrates for the SIF bus.
System chip select. SCS activates the system interface of the TI380C2x for a DIO read or write.
SCS
SDBEN
12
O
H = Not selected
L = Selected
System data bus enable. SDBEN causes the TI380PCI to allow its external data buffers to begin
driving data. SDBEN is accepted during both DIO and DMA.
127
I
H = Keep external data buffers in highĆimpedance state
L = Cause external data buffers to begin driving data
SOWN
SIF bus owned. SOWN signals to the PIF to indicate to external devices that the TI380C2x has
control of the SIF bus. SOWN drives the enable signal of the bus transceiver chips, which drive
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the address and bus control signals.
L = TI380PCI does not have control of the SIF bus.
H = TI380PCI has control of the SIF bus.
† _{The TI380PCI SIF pin names correspond to a subset of the system interface pins on a TI380C2x. Consult the TI380C2x data sheet for more}
information on individual pins. Like-named pins on the TI380PCI and TI380C2x system interfaces are intended to be connected to each other.
‡ _{I = in, O = out}
§ _{Typical bit ordering for Intel and Motorola processor buses}
NOTE 1: The TI380PCI allows driver software to set SBCLK output to a steady high state. This signal is driven to a steady high state during
power-down operations.
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