TI380PCI Datasheet, PDF (13/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
ROM interface (ROMIF) (continued)
When RST is driven high, the value on ROMA[07:00] is latched into the board configuration register in the
TI380PCI configuration space. The value on ROMA[07:00] can be provided by pullup and pulldown resistors
that do not affect operation after reset. This feature allows designers to support jumpers or board stuffing options
sensed by software that reads the board configuration register. If pullup and pulldown registers are not used,
the contents of the board configuration register are undefined after reset.
When the host computer initiates a 32-bit read to the ROMIF, the TI380PCI fetches four bytes from the ROM
and presents the resulting 32-bit DWORD to the PCI bus. The fetches from the ROM start with the least
significant byte, byte 0, followed by bytes 1, 2, and 3. The data is presented to the PCI data bus as shown in
Figure 4.
AD31
AD24 AD23
TI380PCI PCI DATA BUS PINS
AD16 AD15
AD08 AD07
AD00
BYTE 3
BYTE 2
BYTE 1
BYTE 0
ROMA00
ROMA00 ROMA07
ROMA00 ROMA07
TI380PCI ROM DATA BUS PINS
ROMA00 ROMA07
ROMA00
Figure 4. PCI Bus Data
The ROMIF has been designed for operation with EPROM devices with 100 ns access times.
serial EEPROM interface (EIF)
The TI380PCI includes an interface for an optional I²C serial EEPROM. The EEPROM contains the following:
D Bytes 0 × 0 – 0 × 7 contain eight bytes of PCI configuration information that automatically are loaded into
the appropriate PCI configuration register by the 380PCI at power on.
D Byte 0 × 8 is a checksum calculated on bytes 0 – 7. This checksum byte automatically is read at power on
by the TI380PCI. If the checksum read from byte 8 does not agree with the checksum that the 380PCI
calculated from bytes 0 – 7, then the 380PCI sets the ECRCERR and NEP bits in the EEPROM read/write
register in 380PCI configuration space.
D Bytes 0 × 09 – 0 × 10 contain the six bytes of the BIA and two bytes of BIA checksum. The 380PCI reads
these bytes and stores them in an internal register, the contents of which are presented to TI380C2x local
memory bus when the TI380PCI detects an access to the BIA. In this way the TI380PCI emulates the
presence of a BIA ROM on the TI380C2x local memory bus. Note that the TI380PCI does not verify the BIA
checksum.
D Byte 0 × 11 is reserved for use by TI2000 drivers. This byte is not read automatically by the TI380PCI, but
it is read by TI2000 drivers that load bit 0 from this byte into the TI380PCI MISCCTRL register bit 8 and load
bit 1 from this byte into TI380PCI MISCCTRL register bit 9. This byte allows the TI2000 driver to read the
network speed and topology from nonvolatile memory before attempting to access the network.
D Bytes 0 × 12 – 0 × 20 are reserved for future use by the TI380PCI.
D Bytes 0 × 21 – 0 × FF are available for user-defined variable storage.
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