TI380PCI Datasheet, PDF (23/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
base address register (BASE1)—configuration space DWORD address (0x14)
31
Base Address
SPWS020 – AUGUST 1995
43 2 1 0
00000
Prefetchable
Type
Memory Space Indicator
Figure 9. Base Address Register for Memory
The TI380PCI supports only one memory address range decoded down to eight continuous 32-bit locations.
After reset, the value of the address map is set to 0x0. Bits 0 – 4 are read only as 0x0. The LAN subsystem is
expected to reside in I / O space under normal operations for conformance with the TI2000 software, indicating
that this register is not utilized.
interrupt line—configuration space DWORD address (0x3C)
TI380PCI uses a PCI bus interrupt so this register is implemented as an 8-bit read / write register. The value after
reset is 0x00. The least significant four bits are passed to the MISCCTRL register and the TI2000 configuration
register.
interrupt pin—configuration space DWORD address (0x3C)
This is hardwired to 0x01 indicating INTA is used as the interrupt pin.
maximum latency (Max_Lat)—configuration space DWORD address (0x3C)
The TI380C2x has a larger than 1-Kbyte buffer for storing network data; thus, at the maximum network data
rate of 16 Mbps, the TI380C2x can be serviced at intervals greater than 64 µs. This register is loaded with a
value from the EEPROM. If no EEPROM is present, the register is loaded with 0x00.
minimum grant (Min_Gnt)—configuration space DWORD address (0x3C)
This register is loaded with a value from the EEPROM. If no EEPROM is present, the register is loaded with
0x01.
expansion ROM base address register (BASEROM)—configuration space DWORD address (0x30)
31
11 10
10
Expansion ROM Base Address
(Upper 21 Bits)
Reserved
Address Decode Enable
Figure 10. Expansion ROM Base Address Register Layout
The TI380PCI supports an RPL expansion ROM on a PCI bus add-in card. This register is used to configure
the location of the expansion ROM. The BASEROM supports address alignment on a 64Kbyte boundary.
Bits 16 – 31 and bit 0 of BASEROM are read / write, the rest are read only as 0x0. TI380PCI supports 64Kbyte
ROM. Bit 0 is intended to be set by the host.
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