TI380PCI Datasheet, PDF (12/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
address/ data parity checking and generation (continued)
During PCI master cycles, PCIIF is able to handle the following:
D Master-abort termination: due to no DEVSEL response
D Slave-initiated termination: disconnect / retry and slave-abort
D Parity error handling
TI380C2x interface (SIF)
The SIF handles all communications between the TI380C2x and the TI380PCI.
The TI2000 software standard^† requires the TI380PCI SIF to include a configuration register at I / O address
0xE– 0xF. This is the same location as the TI380C2x DIO DMALEN register, therefore, access to the DIO
DMALEN register from the TI380PCI is masked, and the TI380PCI configuration register information is
presented instead.
When there is no DIO access pending, the TI380PCI SIF acknowledges all SBRQ from the TI380C2x and allows
the TI380C2x to control the SIF bus. If the PCIIF initiates a DIO access while the TI380C2x is controlling the
SIF bus and is performing a DMA access, the SIF signals the TI380C2x to relinquish control of the SIF bus and
let the DIO proceed. On completion of the DIO cycle, the SIF logic again grants the SIF bus to the TI380C2x,
if the interrupted DMA sequence is not complete.
The interface between the TI380PCI and the TI380C2x operates in Motorola mode. The interface is designed
so it can operate with drivers that use 8- or 16-bit I/O instructions on the host. Accesses to the SIFDAT,
SIFDAT/INC, and SIFADR registers are ideally made with 16-bit I/O instructions from the host. If a driver has
to perform byte-accesses to these registers, then the odd byte must be accessed before the even byte.
Note that on Intel platforms the INSTR word and the OUTSTR word 16-bit I/O instructions use a little-endian
byte ordering that does not work without additional byte-swapping when used with the TI380PCI Motorola-mode
big-endian interface. These instructions are typically used only in 16-bit pseudo DMA drivers.
For more information on byte operations between the host and the TI380C2x, see the description of DIO
operations on pages 4-16 and 4-28 in the TMS380 Second Generation User’s Guide.
interrupt request
interrupting the PCI host
The SIF takes an SIRQ from the TI380C2x, sends it to the PCIIF, and the PCIIF then translates it into an INTA
on the PCI bus. The generation of INTA on the PCI bus is held off until the data in the TI380PCI FIFO has been
emptied. This interrupt is done to assure data coherency.
clearing the host interrupt request
Driver software running on the host can clear the SIRQ interrupt by writing a 0 to bit 8 of the SIFCMD register
in the TI380C2x. Writing a 1 to this location has no effect (see TI380C2x User’s Guide).
ROM interface (ROMIF)
The ROMIF supports remote program load for PCI LAN adapter cards. This interface supports a 64K-byte ROM
address range aligned on a 64K-byte boundary. Since the PCI bus can access the ROM in any byte order, the
ROMIF reads all 32 bits for each PCI ROM access. This latency is acceptable because the PCI bus does not
execute code out of the ROM. The ROM is normally accessed during system configuration with performance
is not critical. The ROMIF uses either 14 or 16 bits of the address depending on the setting of bit 17 in the
MISCCTRL register. In 14-bit mode, the ROMIF appends two bits to the most significant end of the address from
its internal page register. The TI2000^† software standard requires that writes to the ROM location increment to
the next 16K pages and that the ROM pages be cycled through only once until the next reset. Note that ROMCS
does not go low when the host attempts to write to the EPROM.
† _{TI2000 software standard specification is available from your local TI Sales Office.}
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