TI380PCI Datasheet, PDF (20/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
device identification
The TI380PCI contains the following device identification information in its configuration space.
REGISTER
Vendor ID
Device ID
HEX VALUE
104Ch†
0508h†
Revision ID
01
Header type
00
Class code
028000
† _{These values are defaults and can be overwritten by the}
contents of the optional EEPROM.
COMMAND register—configuration space DWORD address (0x04)
15
10 9 8 7 6 5 4 3 2 1 0
Reserved
0
0
0
Fast Back-to-Back Enable
SERR Enable
Wait Cycle Control
Parity Error Response
VGA Palette Snoop
Memory Write and Invalidate Enable
Special Cycles
Bus Master
Memory Space
I / O Space
Figure 5. Command Register Layout
The COMMAND register provides coarse control over the TI380PCI’s ability to generate and to respond to PCI
cycles. When 0 is written to this register, the device is logically disconnected from the PCI bus for all accesses
except configuration accesses.
The COMMAND register is set to 0 at power up and after hardware reset.
Bit 00: Controls TI380PCI’s response to I / O space accesses. A value of 0 disables TI380PCI’s response. A
value of 1 allows TI380PCI to respond to I / O space accesses.
Bit 01: Controls TI380PCI’s response to memory space accesses. A value of 0 disables TI380PCI’s response.
A value of 1 allows TI380PCI to respond to memory space accesses.
Bit 02: Controls TI380PCI’s ability to act as a master on the PCI bus. A value of 0 disables TI380PCI from
generating PCI accesses. A value of 1 allows the TI380PCI to behave as a bus master. Note that if the automatic
software reset bit in the 380PCI interface control register (0x54) is set to a one then the action of clearing the
bus master bit of the 380PCI command register from one to zero also resets the TI380PCI.
Bit 03: CONTROL[3] allows the LAN subsystem to enter low-power mode following a shutdown broadcast. All
other special cycle messages are ignored. Device drivers must reinitialize and download micro code to the LAN
subsystem when the subsystem exits low-power mode.
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