TI380PCI Datasheet, PDF (14/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
serial EEPROM interface (EIF) (continued)
The user can program several copies of the BIA into the EEPROM user-defined space as a protection against
inadvertent modification of the copy of the BIA at addresses 0x08 – 0x0F.
PARAMETER DESCRIPTION
Vendor ID least significant byte
Vendor ID most significant byte
Device ID least significant byte
Device ID most significant byte
Revision ID
Sub-class
Min_Gnt
Max_Lat
Checksum
Burned-in address
TI2000 reserved byte
Reserved for future use
User defined
Table 1. EIF Configuration Registors
EEPROM BYTE ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12 ... 0x20
0x21 ... 0xFF
DEFAULT VALUE
0x4C
0x10
0x08
0x05
0x10
0x80
0x01
0x00
0x7A
BIA MSbyte
BIA byte
BIA byte
BIA byte
BIA byte
BIA LSbyte
BIA MS checksum
BIA LS checksum
0x01
Reserved
User defined
Systems that do not use an EEPROM should tie the EDC pin low and the EDIO pin high. This action causes
default values to be loaded into the configuration registers as shown in Table 1. EDC and EDIO are sampled
at the deassertion of RST. If EDC is low and EDIO is high at the deassertion of reset, the TI380PCI assumes
that no EEPROM is present in the system.
The default values for the parameters stored in the EEPROM can always be accessed by software because
copies of these values are stored in a series of hardwired registers in the TI380PCI configuration space. These
registers are read only and are unaffected by the process of loading data from the optional EEPROM.
The algorithm that should be used to generate the cyclic redundancy check (CRC) code placed in the serial
EEPROM byte 08 is included here. When the TI380PCI reads the EEPROM after power up, it checks the CRC
in byte 08 to ensure that it was generated with this algorithm. If the CRC from byte 08 of the EEPROM does
not match the CRC calculated from EEPROM bytes 0 – 7, then the TI380PCI sets the NEP and ECRCERR bits
in the EEPROM read/write register. When the NEP and ECRCERR bits are set owing to a CRC mismatch on
the data read from the EEPROM, the TI380PCI still continues to load the data read EEPROM into the PCI
configuration registers. Note that in the event that the EEPROM is unprogrammed, the TI380PCI configuration
registers may be left in an unknown state. In such a case, the EEPROM can be initialized by using PCI BIOS
calls to read the hardwired configuration register addresses associated with each PCI slot. The slot containing
the TI380PCI responds with the contents of the hardwired registers. Once the slot containing the TI380PCI has
been identified, the EEPROM can be programmed using the EEPROM register in the PCI configuration space.
After the next power cycle the TI380PCI loads the contents of the initialized EEPROM.
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