TI380PCI Datasheet, PDF (25/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
miscellaneous control register (MISCCTRL)—configuration space DWORD address (0x40) (continued)
Bits 8 – 9: Speed and topology. These bits are echoed in bits 8 – 9 of TI2000 configuration registers. At reset,
these bits are set to 0x1.
SPEED BIT 9
0
1
0
1
TOPOLOGY BIT 8
0
0
1
1
DESCRIPTION
Full-duplex Ethernet
Ethernet
Token Ring 16 Mbps
Token Ring 4 Mbps
Bit 10: The CONNECTOR bit indicates the connector in use: TI2000 drivers do not currently use this bit;
however, it must always read as 0 if it is not implemented in adapter logic. The value of this bit is presented on
pin DB9 / UTP of the TI380PCI. Upon reset, this bit is 0.
1 = D-Shell (AUI or DB9 )
0 = UTP /10BaseT
Bits 11 – 15: Reserved and is read as 0x9.
Bit 16: Sleep. Setting this bit to a 1 causes the SBCLK and output from the TI380PCI to be driven to a steady
high state. SBCLK is used as SBCLK for the TI380C2x, holding it high causes the TI380C2x to suspend
operations and go into power-saving mode. When this bit changes from a 1 to 0, the SBCLK returns to normal
operation. This bit is set to 0 on reset.
Bit 17: Expansion ROM address mode, 14/ 16. This bit indicates to the ROMIF that it should either use full 16-bit
addressing or support the TI2000 paging protocol. When using TI2000 paging, the ROMIF uses the least
significant 14 bits of the 16-bit ROM address and the most significant two bits are provided by an internal
TI380PCI page register. This bit is set to 0x0 after reset, indicating full 16-bit mode.
Bit 18: This bit is reserved and is set to zero during reset by the TI380PCI. This bit is read as zero and should
always remain set to zero.
Bits 19 – 20: SBCLK divide ratio. These bits specify the relationship between the PCI clock and the TI380C2x’s
SBCLK. After reset, these bits are set to 0x1.
BIT 20
0
0
1
1
BIT 19
0
1
0
1
SBCLK FREQUENCY
PCLK / 1
PCLK / 2
PCLK / 3
PCLK / 4
Bits 21 – 27: Reserved
Bit 28: Address Parity Error is set to 1 when the TI380PCI detects an address-parity error when acting as a PCI
slave. This bit is set to 0 after reset.
Bit 29: Target Reported Parity Error is set to 1 when the TI380PCI receives a data parity error (that is, receives
PERR during a master write and / or detected a parity error during master read). This bit is set to 0 after reset.
Bit 30: Retry Count Expired is set to 1 when the TI380PCI has exceeded the maximum retry count with a master
transaction. This bit is set to 0 after reset.
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