TI380PCI Datasheet, PDF (32/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
timing parameters (5-V signaling environment)
PARAMETER
MIN MAX UNIT
tval
CLK to signal valid delay-bussed signals (see Notes 5, 6, 7)
2
11 ns
tval(ptp) CLK to signal valid delay-point-to-point (see Notes 5, 6, 7)
2
12 ns
ton
Float to active delay (see Note 5)
2
ns
toff
Active to float delay (see Note 5)
28 ns
tsu
Input setup time to CLK-bussed signals (see Notes 7, 8)
7
ns
tsu(ptp) Input setup time to CLK-point-to-point (see Notes 7, 8)
10, 12
ns
th
Input hold time from CLK (see Note 8)
0
ns
trst
Reset active time after power stable (see Note 9)
1
ms
trst-clk Reset active time after CLK stable (see Note 8)
100
µs
trst-off Reset active to output float delay (see Notes 8, 10)
40 ns
NOTES: 5. See timing measurement conditions in the Output Timing Measurement Conditions diagram of the PCI Specification 2.0.
6. Minimum times are measured with 0 pF equivalent load; maximum times are measured with 50 pF equivalent load. Actual test
capacitance can vary, but results should be correlated to these specifications.
7. REQ and GNT are point-to-point signals, and have different output valid delay and input setup times than do bussed signals. GNT
has a setup of 10; REQ has a setup of 12. All other signals are bussed.
8. See timing measurement conditions in the Input Timing Measurement Conditions diagram of the PCI Specification 2.0.
9. RST is asserted and deasserted asynchronously with respect to CLK. Refer to PCI Specifications 2.0 for more information.
10. All output drivers must be floated when RST is active.
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