TI380PCI Datasheet, PDF (6/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
Pin Functions – System Interface^† (Continued)
PIN
NAME
NO.
SRESET
17
SRSX
13
SRS0
14
SRS1
15
SXAL
144
SUDS
123
SDTACK
125
I/O‡
DESCRIPTION
System reset. SRESET is sent to initialize the TI380C2x. It is set low whenever RST goes low or by
a config write to MISCCTRL.
O
H
= No system reset
L
= System reset
Rising edge = Latch bus width for DMA operation
System register select. These outputs are sent to select the word or byte to be transferred during a
system DIO access. The most significant bit is SRSX and the least significant bit is SRS1.
O
MSB
LSB
Registers selected =
SRSX SRS0 SRS1
System extended address latch. SXAL provides the enable pulse that externally latches the most
I
significant 16 bits of the 32-bit system address during DMA. SXAL is activated by the TI380C2x prior
to the first cycle of each block DMA transfer, and thereafter as necessary (whenever an increment of
the DMA address counter causes a carryout of the lower 16 bits).
Upper data strobe. SUDS serves as the active-low upper data strobe. SUDS is an output during DIO
and an input during DMA.§
I/O
H = Not valid data on SADH0 – SADH7 lines
L = Valid data on SADH0 – SADH7 lines
System data transfer acknowledge. The purpose of SDTACK is to indicate to the bus master that a data
transfer is complete. SDTACK is internally synchronized to SBCLK by the TI380C2x. During DMA
cycles, it is asserted before the falling edge of SBCLK in state T2 by the TI380PCI to prevent a wait
I/O
state. SDTACK is an input when the TI380C2x is selected for DIO, and an output otherwise.§
H = System bus NOT ready
L = Data transfer is complete; system bus is ready.
SBERR
Bus error. SBERR corresponds to the bus error signal of the 68000 microprocessor. SBERR is driven
7
O
low during a DMA cycle to indicate to the TI380C2x that the cycle must be terminated. See Section
3.4.5.3 of the TMS380 Second - Generation Token Ring User’s Guide (SPWU005) for more
information.
SLDS
Lower data strobe. SLDS is an output during DIO and an input during DMA. SLDS serves as the
active-low lower data strobe.§
1
I/O
H = Not valid data on SADL0-SADL7 lines
L = Valid data on SADL0-SADL7 lines
SHALT
System halt/bus error retry. If SHALT is asserted along with bus error (SBERR), the adapter retries the
3
O
last DMA cycle. This is the rerun operation as defined in the 68000 specification. See Section 3.4.5.3
of the TMS380 Second - Generation Token Ring User’s Guide (SPWU005) for more information.
SBGR
System bus grant. SBGR serves as an active-low bus grant, as defined in the standard 68000
interface.
5
O
H = System bus not granted
L = System bus granted
System bus request. SBRQ is used to request control of the system bus in preparation for a DMA
transfer. SBRQ is internally synchronized to SBCLK.
SBRQ
129
I
H = System bus not requested
L = System bus requested
† _{The TI380PCI SIF pin names correspond to a subset of the system interface pins on a TI380C2x. Consult the TI380C2x data sheet for more}
information on individual pins. Like-named pins on the TI380PCI and TI380C2x system interfaces are intended to be connected to each other.
‡ _{I = in, O = out}
W ^§ The signal connecting this pin to the TI380C2x also should be connected to a 4.7-k pullup resistor.
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