TI380PCI Datasheet, PDF (18/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
FIFO operation (write cycles)
The TI380PCI BIF snoops the status cycles on the TI380C2x local bus. When the TI380PCI detects a status
code that indicates the start of a DMA write from the TI380C2x to the host computer, the TI380PCI immediately
initiates a DIO read of the DMALEN register in the TI380C2x. When the DMALEN register has been read, the
TI380PCI grants the TI380C2x control of the SIF bus and the DMA write can proceed.
The DMALEN register is not read again until the next DMA transaction starts. During DMA write cycles from
the TI380C2x, the TI380PCI stores one cache line in the FIFO before requesting the PCI bus. It drives data on
the PCI bus as long as it has sufficient data in the FIFO or until it loses the PCI bus. The FIFO control requests
the PCI bus under the following conditions:
D A full cache line is available for writing and the DMA address is aligned on a cache boundary. The PCI bus
cycle is a write-and-invalidate cycle.
D The TI380C2x relinquishes control of the SIF bus owing to completion of a DMA write from the TI380C2x
with DMA data in the TI380PCI FIFO. If the quantity of data in the TI380PCI FIFO is greater than or equal
to the cache line size and the DMA address is aligned on a cache line boundary, the PCI cycles are
write-and-invalidates. If the quantity of data in the TI380PCI FIFO is less than the cache line size or the DMA
address is not aligned on a cache line boundary, the PCI cycles are memory writes.
D A full 32-bit word is available for the PCI bus and the cache line size is zero.
If the host attempts a DIO access during a DMA transfer between the TI380C2x and the host, the TI380PCI
signals the TI380C2x to pause the DMA transfer. When the TI380PCI regains control of the SIF bus, the DIO
access from the host is allowed to complete, and then the TI380PCI allows the DMA transfer to restart and run
to completion. Note that the TI380PCI signals the host to retry the DIO access until the TI380PCI gains control
of the SIF bus and can allow the DIO access to complete. In the case of a DMA write from the TI380C2x to the
host (which is almost complete), the TI380PCI can give up control of the SIF bus prior to transferring the last
data from the FIFO to the host. If the host initiates a DIO access at this time, the DIO access is allowed to
complete immediately, i.e., before the FIFO empties.
FIFO operation (read cycles)
The TI380PCI BIF snoops the status cycles on the TI380C2x local bus. When the TI380PCI detects a status
code that indicates the start of a DMA read by the TI380PCI from the host computer, the TI380PCI immediately
initiates a DIO read of the DMALEN register in the TI380C2x. When the DMALEN register has been read, the
TI380PCI grants the TI380C2x control of the SIF bus, and the DMA read can proceed. The DMALEN register
is not read again until the next DMA transaction starts. The TI380PCI then requests the PCI bus and begins
filling the FIFO. As data is available, it is provided to the TI380C2x. The TI380PCI counts the bytes received
from the PCI bus and decrements its DMA length counter. If the DMA count is not zero, but the TI380C2x
releases the SIF bus, the TI380PCI continues to read data from the PCI bus. The TI380PCI logic terminates
the PCI ownership when the DMA count goes to zero.
The TI380PCI always performs memory-read line commands on the PCI bus regardless of DMA count or
address alignment.
BIA interface
On power up, BIA data is loaded from the EEPROM and held in registers inside the TI380PCI. All the pins on
the local bus of the TI380C2x necessary to sense an access from the TI380C2x to an attached BIA ROM are
connected to the TI380PCI. When the TI380PCI senses an access to the BIA ROM, it drives the BIA data onto
the MADHxx bus, simulating the presence of a BIA ROM on the TI380C2x local bus.
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