TI380PCI Datasheet, PDF (26/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
miscellaneous control register (MISCCTRL)—configuration space DWORD address (0x40) (continued)
Bit 31: Software Reset is a programmable reset. Setting this bit to a 1 causes the SRESET output to pulse low
for a minimum of 14 µs and results in a hard reset to the LAN subsystem. (This function is provided primarily
for hardware and driver-software debug purposes.) This bit is set to 0 after reset. When set to 1, this bit resets
itself to 0 after four PCI clock cycles.
EEPROM read / write register (0 × 48)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rsvd
rsvd
rsvd
rsvd
rsvd
rsvd
rsvd
ECR-
CERR
NEP
ECLK
EEN
EDATA
rsvd
rsvd
rsvd
rsvd
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
ECRCERR
NEP
ECLK
EEN
EDATA
EEPROM CRC error detected. This bit is normally 0 but is set to a 1 if an error is detected in the CRC read from
the EEPROM at power up. If this bit is set, the TI380PCI also sets bit 7, the NEP bit.
EEPROM not present. This bit indicates that the EEPROM interface was disabled either by a pulldown resistor on
the EDIO pin or by the detection of an error in the checksum during the EEPROM download process.
EEPROM SIO Clock: This bit controls the state of the EDC pin.
1 = pin high
0 = pin low
EEPROM enable: This bit controls the direction of the EDIO pin. When this bit is set to a 1, the EDIO pin is driven
with a value in the EDATA bit.
EEPROM data: This bit is used to read or write the EDIO data pin on the EEPROM. When bit 5 is a 1, the
EEPROM data pin is driven with the value of this bit. If bit 5 is a 0, this bit is driven by the level on the EEPROM
EDIO data pin.
380PCI interface control register —configuration space DWORD address (0x54)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits 0 – 15
Reserved; may not
be read as zero.
Bit 16
Automatic
Software Reset
Bits 17 – 31
Reserved; may not
be read as zero.
Figure 12. Interface Control Register
Bits 0 – 15: Reserved may not read as zero.
Bit 16: The automatic software reset controls the impact of writing a zero to the bus master bit (bit 2) in the
TI380PCI command register 0x04. When this bit is set to zero, the TI380PCI resets itself if the host processor
causes a transition from one to zero of the bus master bit. When bit 16 is set to one, the TI380PCI does not reset
itself when the host processor causes a transition from one to zero of the master bus.
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