TI380PCI Datasheet, PDF (24/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
subsystem-specific registers
The TI380PCI contains the following registers in addition to the PCI-prescribed registers.
miscellaneous control register (MISCCTRL)—configuration space DWORD address (0x40)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA Channels
INT
Speed and
Topology
CONNECTOR
Reserved
Sleep
Expansion ROM
Address Mode
Reserved
SBCLK Divide
Ratio
Reserved
Address Parity
Error
Target Reported
Parity Error
Retry Count
Expired
Software Reset
Figure 11. Miscellaneous Control Register
The MISCCTRL is a collection of LAN subsystem control functions. The value of the bit fields in this register
after reset are as indicated.
Bits 0 – 3: DMA channels: DMA channel has no meaning in a PCI context. These four bits also appear in the
TI2000 configuration register where they select between bus master DMA operation and pseudo-DMA
operation as defined by the TI2000 software specification. When this field has the value zero, a TI2000 driver
should operate in pseudo-DMA mode. When the field is nonzero, a TI2000 driver should operate in bus master
DMA mode.
Bits 4 – 7: The four INT bits indicate the interrupt level. At reset, these bits are set to 0x0. They are read only
and echo the least significant bits of the Interrupt Line Register.
24
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443