TI380PCI Datasheet, PDF (16/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
serial EEPROM interface (EIF) (continued)
PARAMETER DESCRIPTION
Vendor ID
Device ID
Revision ID
Subclass
Min_Gnt
Max_Lat
HARDWIRED REGISTER NAME
(CONTAINS READ-ONLY COPY
OF DEFAULT VALUE)
Hardwired vendor ID
Hardwired device ID
Hardwired revision ID
Hardwired subclass
Hardwired Min_Gnt
Hardwired Max_Lat
REGISTER ADDRESS IN TI380PCI
CONFIGURATION SPACE
4C
4C
50
50
50
50
The EEPROM also can be read and written under software control by PCI configuration register 0x48. A typical
I²C EEPROM that can be used with the TI380PCI is the 24C02. EEPROMs that provide external address pins
for identification of several devices on the I²C bus should have these address pins pulled down to logic 0.
burned-in address interface (BIF)
The BIF logic is designed to connect directly to the local memory bus of the TI380C2x. The BIF serves two
purposes:
D Snoops the status cycles on the local memory bus to detect the initialization and completion of DMA
transfers from the TI380C2x.
D Detects accesses to the BIA ROM from the TI380C2x. During a BIA access, the TI380PCI drives data onto
MADH00– 07, emulating a BIA PROM. This eliminates the need for a separate BIA PROM.
in-circuit test NAND tree operation
The terminal function table in this data sheet explains how to use the ICT pins on the TI380PCI to place the
output pins of the TI380PCI in a 3-state mode to allow for in-circuit testing of a PCB.
The TI380PCI also contains a NAND tree that can be used during the in-circuit testing process to verify the
integrity of the solder connections to the TI380PCI. The NAND tree is activiated by latching a control value on
the SADL0–7 pins on the rising edge of the signal applied to the ICT pin.
To activate the NAND tree:
1. Drive and hold ICT low.
2. Drive and hold the MAX0 input low and drive the MAX2 input high. Drive and hold the SADL0–7 pins as
follows:
SADL7
0
SADL6
0
SADL5
0
SADL4
0
SADL3
0
SADL2
0
SADL1
1
SADL0
0
3. While holding the values in step 2, pull the ICT input high to latch the values from step 2.
The connections to the TI380PCI can now be tested with the NAND tree. The NAND tree can be deactivated
by repeating steps 1 through 3 with the data applied to the SADL0–7 pins in step 2 set as follows:
SADL7
0
SADL6
0
SADL5
0
SADL4
0
SADL3
0
SADL2
0
SADL1
0
SADL0
0
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