TI380PCI Datasheet, PDF (10/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
PIN
NAME
NO.
I/O†
IRDY
56
I /O
PCLK
23
I
PERR
61
I/O
REQ
RST
26
O
21
I
SERR
STOP
62
I/O
60
I/O
TRDY
57
I/O
† _{I = in, O = out}
Pin Functions – PCI Interface (Continued)
DESCRIPTION
Initiator ready. IRDY indicates the bus master’s ability to complete the current data phase of the
transaction. If a data phase is completed on any clock, both IRDY and TRDY are sampled and asserted.
During a write, IRDY indicates that valid data is present on AD31 – AD00. During a read, it indicates the
master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted
together.
Clock. PCLK provides timing for all transactions on the PCI bus. All other PCI signals, except RST and
INTA, are sampled on the rising edge of PCLK. PCLK is used to generate the SBCLK signal that goes to
the TI380C2x.
Parity error. PERR is for the reporting of data parity errors during all transactions. It is driven active by the
agent receiving data two clocks following the data when a data parity error is detected. The minimum
duration of PERR is one clock for each data phase that a data parity error is detected.
There are no special conditions when a PERR can be lost or when reporting of an error can be delayed.
An agent cannot report a PERR until it has claimed the access by asserting DEVSEL and completing a
data phase.
Request. REQ indicates to the arbiter that TI380PCI desires use of the bus. REQ is a point-to-point signal.
Reset. RST is used to hard reset the LAN subsystem, including TI380C2x and the TI380PCI.
To prevent AD, C/BE, and PAR signals from floating during reset, the central device can drive these lines
during reset (bus parking) but only to a logic low level; they can not be driven high.
System error. SERR, when enabled, reports address parity errors or any other system error where the
result is catastrophic. The assertion of SERR is synchronous to the clock and meets the setup and hold
times of all PCI signals.
Stop. STOP indicates the current slave is requesting the master to stop the current transaction.
Target ready. TRDY indicates the target agent’s (the TI380PCI) ability to complete the current data phase
of the transaction. If a data phase is completed on any clock, both TRDY and IRDY are sample asserted.
During a read, TRDY indicates that valid data is present on AD31 – AD00. During a write, it indicates that
the target is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted
together.
PIN
NAME
NO.
EDIO
111
EDC
122
† _{I = in, O = out}
Pin Functions – Serial EEPROM Interface
I/O†
DESCRIPTION
EEPROM data input / output is a bidirectional signal used to transfer data into or out of the EEPROM
I/O
memory. Note I2C memory devices typically require a pullup resistor to VCC on this line. This is an open
drain output. If the optional EEPROM is not present, EDIO should be tied high.
EEPROM clock signal used to synchronize all data in and data out of the memory. I2C memory devices
O
typically require a pullup resistor to VCC on this line. If the optional EEPROM is not present, EDC should
be tied low.
10
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443