TI380PCI Datasheet, PDF (19/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
TI380PCI registers
The TI380PCI supports a number of registers to facilitate communications between the host computer and the
token-ring LAN subsystem. It also performs address translation to map TI380C2x DIO registers into host
computer memory or I / O space. Table 2 describes the configuration space registers implemented within the
TI380PCI. The registers shown as shaded are autoloaded from an external serial EEPROM at power up.
DWORD ADDRESS
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x44
0x48
0x4C
0x50
0x54
0x58–0xFF
Table 2. Configuration Space Header
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Device ID
Vendor ID
Status
Command
Base-Class
Sub-Class
Revision ID
Header Type
Latency Timer
Cache Line Size
Base Address I/O
Base Address Memory
Reserved (returns 0)
Reserved (returns 0)
Reserved (returns 0)
Reserved (returns 0)
Reserved (returns 0)
Reserved (returns 0)
Expansion ROM Base Address
Reserved (returns 0)
Reserved (returns 0)
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
Miscellaneous Control (MISCCTRL) Register
Board Config Register
Reserved (returns 0)
EEPROM
Hardwired DEVICE ID
Hardwired VENDOR ID
H/W Subclass
H/W Max Lat
H/W Min Gnt
H/W Revision ID
380PCI Interface Control Register
Reserved (returns 0 when read)
READ/WRITE
R
R/W
R
R/W
R/W
R/W
R
R
R
R
R
R
R/W
R
R
R/W
R/W
R
R/W
R
R
R
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
19