TI380PCI Datasheet, PDF (17/36 Pages) Texas Instruments – PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
TI380PCI device operation
TI380PCI behavior as a PCI bus target
The PCIIF in the TI380PCI acts as an I/O slave to the PCI bus after power up and when the LAN subsystem
is not the PCI bus master. It monitors and decodes PCI commands for memory, I/O, and configuration accesses.
Enabling of memory and I/O accesses are performed by setting and cleaning bits in the COMMAND register.
TI380PCI behavior as a PCI bus master
The TI380PCI requests to become a master on the PCI bus after the TI380C2x initiates a DMA transfer to the
TI380PCI. The TI380C2x begins a DMA series by asserting SBRQ and requesting its own system interface bus.
The TI380PCI performs a DIO access to the TI380C2x and reads the DMA length before granting the SIF bus
to the TI380C2x. (Note that the read cycle occurs only on the first transaction of the DMA access). If the
TI380C2x has requested DMA write access and no DIO access from the PCI bus is pending, the TI380PCI
acknowledges the request and latches the DMA address and completes the write cycle from the TI380C2x to
start filling the FIFO. Subsequent writes continue to fill the FIFO. When the FIFO contains 60 bytes of data, the
PCIIF logic arbitrates for the PCI bus and transfer the data in a burst sequence.
If the access is a read access, the TI380PCI acknowledges the request and latches the DMA address. It then
initiates a read access on the PCI bus. If the DMA length exceeds the cache line size, as defined by the contents
of the TI380PCI cache line size configuration register, then the read access on the PCI bus is a burst read. As
data is available from the PCI bus, it is provided to the TI380C2x. Since the PCI bus has a higher bandwidth
than the TI380C2x SIF bus, the 64-byte FIFO in the TI380PCI fills as the burst read continues. If the FIFO fills
before the DMA length is reached, the PCI master relinquishes the bus until the FIFO is almost empty.
If a DIO conflict occurs while the DMA is in progress, the TI380PCI forces the TI380C2x off the SIF bus to allow
the DIO to complete. The DMA operation resumes at the point it was interrupted and continues until completion.
removal of TI380PCI as bus master
The TI380PCI is removed as the PCI bus master under two conditions:
D target-inititiated retry and/or termination
D master-initiated termination as no PCI agent asserted DEVSEL.
TI380PCI behavior on the SIF bus
SIF behavior as a SIF master
The TI380PCI SIF logic masters the TI380C2x system interface to translate signals from the PCIIF into
TI380C2x control signals and relays TI380C2x return signals to the PCIIF.
SIF behavior as a slave
The SIF acts as a slave when the TI380C2x is engaged in DMA operations. During DMA transfers, other PCI
masters can access the TI380C2x’s DIO registers. The TI380PCI retries all accesses from the PCI bus while
posting a preempt to the TI380PCI SIF. When the TI380PCI SIF receives the preempt, it signals the TI380C2x
to relinquish the SIF bus at the earliest opportunity and does not grant the TI380C2x the SIF bus until the
preempt is removed.
FIFO control
The 64-byte FIFO serves to reduce the bandwidth demand on the PCI bus from the TI380PCI. It is used only
when the TI380C2x is functioning as a PCI bus master during DMA accesses.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
17