DS90UR124Q_14 Datasheet, PDF (9/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
t_TCP
TCLK
V_DD/2
V_DD/2
V_DD/2
t_DIS
t_DIH
DIN [0:23] _VDD/2
Setup
Hold
V_DD/2
V_DD
0V
Figure 5. Serializer Setup/Hold Times
Parasitic package and
Trace capacitance
DEN ^VCC^/2
(single-ended)
0V
D_OUT±
(differential)
200 mV
DEN ^VCC^/2
(single-ended)
0V
200 mV
D_OUT±
(differential)
DEN
D_OUT+
D_OUT-
5 pF
100:
CLK1
t_LZD
V_CC/2
CLK1
t_TCP
t_TCP
t_ZLD
t_ZHD
DCA
DCA _{DCA DCA}
$OO GDWD ³0´V
DCA DCA DCA DCA
t_HZD
V_CC/2
DCA ^{DCA DCA DCA}
$OO GDWD ³1´V
DCA DCA DCA DCA
t_TCP
t_TCP
CLK0
CLK0
Figure 6. Serializer TRI-STATE Test Circuit and Delay
0V
200 mV
0V
200 mV
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