DS90UR124Q_14 Datasheet, PDF (25/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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3.3V
C1
DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
DS90UR124 (DES)
VDD
VDD
C5
VDD
VDD
C7
3.3V
C3
VDD
VDD
C2
C6
VDD
VDD
C8
C4
C9
Serial
LVDS
R1
Interface
C10
GPO if used, or tie High (ON)
GPOs if used,
or tie Low (OFF)
3.3V
Notes:
RPWDNB = System GPO
REN = High (ON)
RRFB = High (Rising edge)
RAOFF = Low (Default)
PTOSEL = Low (Defaut)
SLEW = Low (Default)
RES0 = Low
BISTEN = GPO or Low
BISTM = GPO or Low
RIN+
RIN-
RPWDNB
BISTEN
BISTM
REN
RRFB
RAOFF
PTOSEL
SLEW
RES0(11)
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
ROUT21
ROUT22
ROUT23
RCLK
LOCK
PASS
LVCMOS
Parallel
Interface
C1 to C4 = 0.1 PF
C5 to C8 = 0.01 PF (optional)
C9 to C10 = 100 nF;
50WVDC, NPO or X7R
R1 = 100:
Figure 22. DS90UR124 Typical Application Connection
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SERDES devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
Copyright © 2006–2013, Texas Instruments Incorporated
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