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| DS90UR124Q_14 Datasheet, PDF (12/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset | |||
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DS90UR124Q, DS90UR241Q
SNLS231N â SEPTEMBER 2006 â REVISED MARCH 2013
www.ti.com
REN
500:
VREF
CL = 8 pF
+
-
VREF = VDD/2 for tZLR or tLZR,
VREF = 0V for tZHR or tHZR
NOTE:
CL includes instrumentation and fixture capacitance within 6 cm of ROUT [23:0].
VOH
REN
VOL
VDD/2
tLZR
VDD/2
tZLR
VOL
ROUT [23:0]
VOH
tHZR
VOL + 0.5V
tZHR
VOL + 0.5V
VOH - 0.5V
VOH + 0.5V
Figure 13. Deserializer TRI-STATE Test Circuit and Timing
2.0V
PWDN
RIN±
tDSR
0.8V
}v[Å¡ Å
LOCK TRI-STATE
ROUT [0:23]
TRI-STATE
TRI-STATE
tHZR or tLZR
TRI-STATE
RCLK
TRI-STATE
TRI-STATE
REN
Figure 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
12
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Product Folder Links: DS90UR124Q DS90UR241Q
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