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| DS90UR124Q_14 Datasheet, PDF (13/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset | |||
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www.ti.com
RCLK
VDD/2
DS90UR124Q, DS90UR241Q
SNLS231N â SEPTEMBER 2006 â REVISED MARCH 2013
tRCP
tRDC
tRDC
VDD/2
tROS
tROH
ROUT [7:0]
(group 1)
VDD/2
| -2 UI
Data Valid
Before RCLK
Data Valid
After RCLK
tROS
tROH
VDD/2
| +2 UI
ROUT [15:8]
(group 2)
VDD/2
Data Valid
Before RCLK
Data Valid
After RCLK
VDD/2
| -1 UI
tROS
tROH
| +1 UI
ROUT [23:16]
(group 3)
VDD/2
Data Valid
Before RCLK
Data Valid
After RCLK
VDD/2
| +1 UI
| -1 UI
Figure 15. Deserializer Setup and Hold Times and PTO, PTOSEL = H
ROUT
(Ideal)
½ Symbol ½ Symbol
RCLK
ROUT
GRP1
1 + 3/28 Symbol
1 - 2/28 Symbol
1 + 3/28 Symbol
1 - 4/28 Symbol
2 UI EARLY
1 UI LATE
1 UI EARLY
2 UI LATE
Group 1 will be latched internally by sequence of (early 2UI, late 1UI, early 1UI, late 2UI)
Group 2 will be latched internally by sequence of (late 1UI, early 1UI, late 2UI, early 2UI)
Group 3 will be latched internally by sequence of (early 1UI, late 2UI, early 2UI, late 1UI)
2 UI EARLY
Figure 16. Deserializer Setup and Hold Times and PTO Spread, PTOSEL = L
Copyright © 2006â2013, Texas Instruments Incorporated
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Product Folder Links: DS90UR124Q DS90UR241Q
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