DS90UR124Q_14 Datasheet, PDF (23/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
LVCMOS
Parallel
Interface
GPOs if used, or tie High (ON)
3.3V
Notes:
TPWDNB = System GPO
R2
DEN = High (ON)
TRFB = High (Rising edge)
RAOFF = Low (Default)
VODSEL = Low (500 mV)
PRE = Rpre
RES0 = Low
DS90UR241 (SER)
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
VDD
VDD
VDD
VDD
VDD
VDD
DIN16
DIN17
DIN18
DIN19
DIN20
DIN21
DIN22
DIN23
DOUT+
TCLK
TPWDNB
DEN
TRFB
PRE
VODSEL
RAOFF
RES0(3)
DOUT-
VSS
VSS
VSS
VSS
VSS
VSS
3.3V
C4
C1
C5
C2
C6
C3
C7
R1
C8
Serial
LVDS
Interface
C1 to C3 = 0.1 PF
C4 to C6 = 0.01 PF (optional)
C7 to C8 = 100 nF 50WVDC, NPO or X7R
R1 = 100 :
R2 = Open (OFF)
or Rpre 8 6 k: (ON) (cable specific)
Figure 20. DS90UR241 Typical Application Connection
POWER CONSIDERATIONS
An all LVCMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally,
the constant current source nature of the LVDS outputs minimize the slope of the speed vs. I_DD curve of
LVCMOS designs.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably recover data. Various environmental and systematic factors include:
• Serializer: V_DD noise, TCLK jitter (noise bandwidth and out-of-band noise)
• Media: ISI, V_CM noise
• Deserializer: V_DD noise
For a graphical representation of noise margin, please see Figure 17.
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