DS90UR124Q_14 Datasheet, PDF (10/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
PWDWN
2.0V
TCLK
D_OUT±
t_PLD
TRI-STATE
t_ZHD or
t_ZLD
Output
Active
0.8V
t_HZD or
t_LZD
TRI-STATE
Figure 7. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays
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D_IN
SYMBOL N
TCLK
SYMBOL N+1
SYMBOL N+2
t_SD
SYMBOL N+3
D_OUT0-23
DCA, DCB
STOP START
STOP START
STOP START
STOP START
STOP
SYMBOL N-4 ^{BIT BIT} SYMBOL N-3 ^{BIT BIT} SYMBOL N-2 ^{BIT BIT} SYMBOL N-1 ^{BIT BIT} SYMBOL N ^BIT
012
23
012
23
012
23
012
23
012
23
Figure 8. Serializer Delay
Ideal Data Bit
Beginning
Ideal Data Bit
End
TxOUT_E_O
t_BIT(1/2 UI)
t_BIT(1/2 UI)
Ideal Center Position (t_BIT/2)
t_BIT (1 UI)
Figure 9. Transmitter Output Eye Opening (TxOUT_E_O)
10
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