DS90UR124Q_14 Datasheet, PDF (5/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
www.ti.com
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
ELECTRICAL CHARACTERISTICS^(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min Typ Max Unit
SER/DES SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
I_DDT
Serializer
R_L = 100Ω, PRE = OFF,
Total Supply Current
RAOFF = H, VODSEL = L
(includes load current)
f = 43 MHz,
CHECKER BOARD Pattern
Figure 1⁽⁴⁾
60 85 mA
R_L = 100Ω, PRE = 12 kΩ,
RAOFF = H, VODSEL = L
65 90 mA
R_L = 100Ω, PRE = OFF,
RAOFF = H, VODSEL = H
f = 43 MHz,
RANDOM pattern
66 90 mA
I_DDTZ
Serializer
Supply Current Power-
down
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
45 µA
I_DDR
Deserializer
C_L = 4 pF,
Total Supply Current
SLEW = H
(includes load current)
f = 43 MHz,
CHECKER BOARD
Pattern LVCMOS Output
Figure 2⁽⁴⁾
85 105 mA
C_L = 4 pF,
SLEW = H
f = 43 MHz,
RANDOM pattern
LVCMOS Output
80 100 mA
I_DDRZ
Deserializer
Supply Current Power-
down
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
R_IN+/R_IN-= 0V)
50 µA
(4) Figure 1, Figure 2, Figure 8, Figure 12 and Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Serializer Input Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
t_TCP
t_TCIH
t_TCIL
t_CLKT
t_JIT
Parameter
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
Conditions
Figure 5⁽¹⁾
Figure 4⁽²⁾
f = 43MHz⁽³⁾
f = 33MHz
Min
23.25
0.3T
0.3T
Typ
T
0.5T
0.5T
2.5
(1) Figure 5, Figure 15 and Figure 16 show a rising edge data strobe (TCLK IN/RCLK OUT).
(2) Specification is guaranteed by characterization and is not tested in production.
(3) t_JIT (@BER of 10e-9) specifies the allowable jitter on TCLK. t_JIT not included in TxOUT_E_O parameter.
Max
200
0.7T
0.7T
±100
±130
Units
ns
ns
ns
ns
ps
ps
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