DS90UR124Q_14 Datasheet, PDF (11/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
24
D_IN
D_OUT+
R_L
20194528 _DOUT-
TCLK
VOD = (D_OUT+) – (D_OUT−)
Differential output signal is shown as (D_OUT+) – (D_OUT−), device in Data Transfer mode.
Figure 10. Serializer V_OD Diagram
Deserializer
4 pF
lumped
80%
20%
80%
20%
t_CLH
t_CHL
Figure 11. Deserializer LVCMOS Output Load and Transition Times
R_IN0-23
DCA, DCB
RCLK
START
STOP START
STOP START
STOP START
STOP
BIT _{SYMBOL N} BIT BIT _{SYMBOL N+1} BIT BIT _{SYMBOL N+2} BIT BIT _{SYMBOL N+3} BIT
012
23
012
23
012
23
012
23
t_DD
R_OUT0-23
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
Figure 12. Deserializer Delay
SYMBOL N
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