DS90UR124Q_14 Datasheet, PDF (16/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
DS90UR124 Pin Diagram
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PTOSEL
49
RES0
50
V_DD
51
V_SS
52
R_IN+
53
R_IN-
54
RRFB
55
V_SS
56
V_DD
57
V_SS
58
V_DD
59
REN
60
BISTEN
61
BISTM
62
RAOFF
63
SLEW
64
PTO GROUP 1
DS90UR124
PTO GROUP 3
32
V_DD
31
V_SS
30
R_OUT[8]
29
R_OUT[9]
28
R_OUT[10]
27
R_OUT[11]
26
V_DD
25
V_SS
24
RCLK
23
LOCK
22
R_OUT[12]
21
R_OUT[13]
20
R_OUT[14]
19
R_OUT[15]
18
RES0
17
RES0
Figure 19. Deserializer - DS90UR124
TOP VIEW
DS90UR124 Deserializer Pin Descriptions
Pin # Pin Name
I/O/PWR
Description
LVCMOS PARALLEL INTERFACE PINS
35-38, R_OUT[7:0]
41-44
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 1
19-22, R_OUT[15:8]
27-30
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 2
7-10, R_OUT[23:16]
13-16
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 3
24
RCLK
LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
55
RRFB
60
REN
LVCMOS_I
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; R_OUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; R_OUT LVCMOS Outputs strobed on the Falling Clock Edge.
Receiver Data Enable
REN = H; R_OUT[23-0] and RCLK are Enabled (ON).
REN = L; R_OUT[23-0] and RCLK are Disabled (OFF), Receiver R_OUT[23-0] and RCLK Outputs are
in TRI-STATE, PLL still operational and locked to TCLK.
48
RPWDNB
LVCMOS_I
Receiver Power Down Bar
RPWDNB = H; Receiver is Enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), R_OUT[23-0], RCLK, and LOCK are in
TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
49
PTOSEL
LVCMOS_I
Progressive Turn On Operation Selection
PTO = H; R_OUT[23:0] are grouped into three groups of eight, with each group switching about ±1
UI to ±2 UI apart relative to RCLK. (Figure 15)
PTO = L; PTO Spread Mode, R_OUT[23:0] outputs are spread ±1 UI to ±2 UI and RCLK spread ±1
UI. (Figure 16) See Applications Informations section for more details.
16
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