DS90UR124Q_14 Datasheet, PDF (1/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
www.ti.com
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
DS90UR124Q DS90UR241Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and
Deserializer Chipset
Check for Samples: DS90UR124Q, DS90UR241Q
FEATURES
1
•2 Supports Displays with 18-bit Color Depth
• 5MHz to 43MHz Pixel Clock
• Automotive Grade Product AEC-Q100 Grade 2
Qualified
• 24:1 Interface Compression
• Embedded Clock with DC Balancing Supports
AC-coupled Data Transmission
• Capable to Drive up to 10 Meters Shielded
Twisted-pair Cable
• No Reference Clock Required (Deserializer)
• Meets ISO 10605 ESD - Greater than 8 kV HBM
ESD Structure
• Hot Plug Support
• EMI Reduction - Serializer Accepts Spread
Spectrum Input; Data randomization and
shuffling on serial link; Deserializer provides
Adjustable PTO (progressive turn-on) LVCMOS
outputs
• @Speed BIST (built-in self test) to validate
LVDS transmission path
• Individual power-down controls for both
Transmitter and Receiver
• Power supply range 3.3V ± 10%
• 48-pin TQFP package for Transmitter and 64-
pin TQFP package for Receiver
• Temperature range -40°C to +105°C
• Backward Compatible Mode with
DS90C241/DS90C124
APPLICATIONS
• Automotive Central Information Display
• Automotive Instrument Cluster Display
• Automotive Heads-Up Display
• Remote Camera-based Driver Assistance
Systems
DESCRIPTION
The DS90UR241/124 Chipset translates a 24-bit
parallel bus into a fully transparent data/control FPD-
Link II LVDS serial stream with embedded clock
information. This chipset is ideally suited for driving
graphical data to displays requiring 18-bit color depth
- RGB666 + HS, VS, DE + 3 additional general
purpose data channels. This single serial stream
simplifies transferring a 24-bit bus over PCB traces
and cable by eliminating the skew problems between
parallel data and clock paths. It saves system cost by
narrowing data paths that in turn reduce PCB layers,
cable width, and connector size and pins.
The DS90UR241/124 incorporates FPD-Link II LVDS
signaling on the high-speed I/O. FPD-Link II LVDS
provides a low power and low noise environment for
reliably transferring data over a serial transmission
path. By optimizing the Serializer output edge rate for
the operating frequency range EMI is further reduced.
In addition, the device features pre-emphasis to boost
signals over longer distances using lossy cables.
Internal DC balanced encoding/decoding is used to
support AC-Coupled interconnects. Using TI’s
proprietary random lock, the Serializer’s parallel data
are randomized to the Deserializer without the need
of REFCLK.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated