DS90UR124Q_14 Datasheet, PDF (15/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
www.ti.com
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
DS90UR241 Serializer Pin Descriptions
Pin # Pin Name
I/O/PWR
Description
LVCMOS PARALLEL INTERFACE PINS
4-1,
48-44,
41-32,
29-25
D_IN[23:0]
LVCMOS_I Transmitter Parallel Interface Data Input Pins. Tie LOW if unused, do not float.
10
TCLK
LVCMOS_I Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
CONTROL AND CONFIGURATION PINS
9
TPWDNB
LVCMOS_I Transmitter Power Down Bar
TPWDNB = H; Transmitter is Enabled and ON
TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver D_OUT (+/-) Outputs are in
TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
24
VODSEL
LVCMOS_I
VOD Level Select
VODSEL = L; LVDS Driver Output is ±500 mV (R_L = 100Ω)
VODSEL = H; LVDS Driver Output is ±900 mV (R_L = 100Ω)
For normal applications, set this pin LOW. For long cable applications where a larger VOD is
required, set this pin HIGH.
18
DEN
LVCMOS_I
Transmitter Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver D_OUT (+/-) Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
23
PRE
LVCMOS_I
Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor R_PRE. Resistor value
determines pre-emphasis level. Recommended value R_PRE ≥ 6 kΩ; I_max = [48 / R_PRE], R_PREmin =
6 kΩ
11
TRFB
LVCMOS_I
Transmitter Clock Edge Select Pin
TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge.
TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge
12
RAOFF
LVCMOS_I
Randomizer Control Input Pin
RAOFF = H, Backwards compatible mode for use with DS90C124 Deserializer.
RAOFF = L; Additional randomization ON (Default), Selects 2E7 LSFR setting.
See Table 1 for more details.
5, 8, RES0
13
LVCMOS_I Reserved. This pin MUST be tied LOW.
LVDS SERIAL INTERFACE PINS
20
D_OUT+
LVDS_O
Transmitter LVDS True (+) Output.
This output is intended to be loaded with a 100Ω load to the D_OUT+ pin. The interconnect should
be AC Coupled to this pin with a 100 nF capacitor.
19
D_OUT−
LVDS_O
Transmitter LVDS Inverted (-) Output
This output is intended to be loaded with a 100Ω load to the D_OUT-pin. The interconnect should be
AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
22
VDD
VDD
Analog Voltage Supply, LVDS Output POWER
21
VSS
GND
Analog Ground, LVDS Output GROUND
16
VDD
VDD
Analog Voltage Supply, VCO POWER
17
VSS
GND
Analog Ground, VCO GROUND
14
VDD
VDD
Analog Voltage Supply, PLL POWER
15
VSS
GND
Analog Ground, PLL GROUND
30
VDD
VDD
Digital Voltage Supply, Serializer POWER
31
VSS
GND
Digital Ground, Serializer GROUND
7
VDD
VDD
Digital Voltage Supply, Serializer Logic POWER
6
VSS
GND
Digital Ground, Serializer Logic GROUND
42
VDD
VDD
Digital Voltage Supply, Serializer INPUT POWER
43
VSS
GND
Digital Ground, Serializer Input GROUND
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15
Product Folder Links: DS90UR124Q DS90UR241Q