DS90UR124Q_14 Datasheet, PDF (22/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
APPLICATION INFORMATION
www.ti.com
USING THE DS90UR241 AND DS90UR124
The DS90UR241/DS90UR124 Serializer/Deserializer (SERDES) pair sends 24 bits of parallel LVCMOS data
over a serial LVDS link up to 1.03 Gbps. Serialization of the input data is accomplished using an on-board PLL at
the Serializer which embeds clock with the data. The Deserializer extracts the clock/control information from the
incoming data stream and deserializes the data. The Deserializer monitors the incoming clock information to
determine lock status and will indicate lock by asserting the LOCK output high.
DISPLAY APPLICATION
The DS90UR241/124 chipset is intended for interface between a host (graphics processor) and a Display. It
supports an 18-bit color depth (RGB666) and up to 1280 X 480 display formats. In a RGB666 configuration 18
color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) along with three
spare bits are supported across the serial link with PCLK rates from 5 to 43 MHz.
TYPICAL APPLICATION CONNECTION
Figure 20 shows a typical application of the DS90UR241 Serializer (SER). The LVDS outputs utilize a 100 ohm
termination and 100nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins.
At a minimum, three 0.1uF capacitors should be used for local bypassing. A system GPO (General Purpose
Output) controls the TPWDNB pin. In this application the TRFB pin is tied High to latch data on the rising edge of
the TCLK. The DEN signal is not used and is tied High also. The application is to the companion Deserializer
(DS90UR124) so the RAOFF pin is tied low to scramble the data and improve link signal quality. In this
application the link is typical, therefore the VODSEL pin is tied Low for the standard LVDS swing. The pre-
emphasis input utilizes a resistor to ground to set the amount of pre-emphasis desired by the application.
Figure 22 shows a typical application of the DS90UR124 Deserializer (DES). The LVDS inputs utilize a 100 ohm
termination and 100nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins.
At a minimum, four 0.1uF capacitors should be used for local bypassing. A system GPO (General Purpose
Output) controls the RPWDNB pin. In this application the RRFB pin is tied High to strobe the data on the rising
edge of the RCLK. The REN signal is not used and is tied High also. The application is to the companion
Serializer (DS90UR241) so the RAOFF pin is tied low to descramble the data. Output (LVCMOS) signal quality is
set by the SLEW pin, and the PTOSEL pin can be used to reduce simultaneous output switching by introducing a
small amount of delay between output banks.
22
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR124Q DS90UR241Q