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| DS90UR124Q_14 Datasheet, PDF (14/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset | |||
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DS90UR124Q, DS90UR241Q
SNLS231N â SEPTEMBER 2006 â REVISED MARCH 2013
Ideal Data Bit
Beginning
Sampling
Window
Ideal Data Bit
End
RxIN_TOL -L
RxIN_TOL -R
Ideal Center Position (tBIT/2)
tBIT (1 UI)
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
Figure 17. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
DS90UR241 Pin Diagram
www.ti.com
DIN[10]
37
DIN[11]
38
DIN[12]
39
DIN[13]
40
DIN[14]
41
VDD
42
VSS
43
DIN[15]
44
DIN[16]
45
DIN[17]
46
DIN[18]
47
DIN[19]
48
DS90UR241
24
VODSEL
23
PRE
22
VDD
21
VSS
20
DOUT+
19
DOUT-
18
DEN
17
VSS
16
VDD
15
VSS
14
VDD
13
RES0
Figure 18. Serializer - DS90UR241
TOP VIEW
14
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Copyright © 2006â2013, Texas Instruments Incorporated
Product Folder Links: DS90UR124Q DS90UR241Q
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