DS90UR124Q_14 Datasheet, PDF (6/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
www.ti.com
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
t_LLHT
t_LHLT
t_DIS
t_DIH
t_HZD
t_LZD
t_ZHD
t_ZLD
t_PLD
t_SD
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
D_IN (0:23) Setup to TCLK
D_IN (0:23) Hold from TCLK
D_OUT ± HIGH to TRI-STATE Delay
D_OUT ± LOW to TRI-STATE Delay
D_OUT ± TRI-STATE to HIGH Delay
D_OUT ± TRI-STATE to LOW Delay
Serializer PLL Lock Time
Serializer Delay
R_L = 100Ω, VODSEL = L,
C_L = 10 pF to GND, Figure 3
R_L = 100Ω, C_L = 10 pF to GND⁽¹⁾
Figure 5⁽²⁾
R_L = 100Ω,
C_L = 10 pF to GND⁽³⁾
Figure 6
R_L = 100Ω
R_L = 100Ω, PRE = OFF,
RAOFF = L, TRFB = H,
Figure 8⁽⁴⁾
4
4
3.5T+2
R_L = 100Ω, PRE = OFF,
RAOFF = L, TRFB = L,
Figure 8⁽⁴⁾
3.5T+2
TxOUT_E_O TxOUT_Eye_Opening.
TxOUT_E_O centered on (tBIT/)2
5 MHz–43 MHz,
R_L = 100Ω, C_L = 10 pF to GND,
RANDOM pattern^(5)(6)(7)
Figure 9
0.76
Typ
Max
Units
245
550
ps
264
550
ps
ns
ns
10
15
ns
10
15
ns
75
150
ns
75
150
ns
10
ms
3.5T+10
ns
3.5T+10
ns
0.84
UI
(1) Specification is guaranteed by characterization and is not tested in production.
(2) Figure 5, Figure 15 and Figure 16 show a rising edge data strobe (TCLK IN/RCLK OUT).
(3) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
(4) Figure 1, Figure 2, Figure 8, Figure 12 and Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
(5) t_JIT (@BER of 10e-9) specifies the allowable jitter on TCLK. t_JIT not included in TxOUT_E_O parameter.
(6) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
(7) TxOUT_E_O is affected by pre-emphasis value.
6
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