DS90UR124Q_14 Datasheet, PDF (19/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
www.ti.com
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream (Figure 24).
The CLK1 bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded
clock bits in the serial stream. DCB functions as the DC Balance control bit. It does not require any pre-coding of
data on transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal
lines. This bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used to
validate data integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and
automatically performed within Serializer and Deserializer.
The chipset supports clock frequency ranges of 5 MHz to 43 MHz. Every clock cycle, 24 databits are sent along
with 4 additional overhead control bits. Thus the line rate is 1.20 Gbps maximum (140Mbps minimum). The link is
extremely efficient at 86% (24/28). Twenty five (24 data + 1 clock) plus associated ground signals are reduced to
only 1 single LVDS pair providing a compression ratio of better then 25 to 1.
In the serialized data stream, data/embedded clock & control bits (24+4 bits) are transmitted from the Serializer
data output (DOUT±) at 28 times the TCLK frequency. For example, if TCLK is 43 MHz, the serial rate is 43 x 28
= 1.20 Giga bits per second. Since only 24 bits are from input data, the serial “payload” rate is 24 times the
TCLK frequency. For instance, if TCLK = 43 MHz, the payload data rate is 43 x 24 = 1.03 Gbps. TCLK is
provided by the data source and must be in the range of 5 MHz to 43 MHz nominal. The Serializer outputs
(DOUT±) can drive a point-to-point connection as shown in Figure 23. The outputs transmit data when the enable
pin (DEN) is high and TPWDNB is high. The DEN pin may be used to TRI-STATE the outputs when driven low.
When the Deserializer channel attains lock to the input from a Serializer, it drives its LOCK pin high and
synchronously delivers valid data and recovered clock on the output. The Deserializer locks onto the embedded
clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin.
The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high,
data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the
RRFB input. ROUT[23:0], LOCK and RCLK outputs will each drive a maximum of 4 pF load with a 43 MHz clock.
REN controls TRI-STATE for ROUTn and the RCLK pin on the Deserializer.
RESYNCHRONIZATION
If the Deserializer loses lock, it will automatically try to re-establish lock. For example, if the embedded clock
edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The Deserializer
then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock
edge, identifies it and then proceeds through the locking process.
The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is high, the data is valid.
The system may monitor the LOCK pin to determine whether data on the ROUT is valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power
when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into power down
mode, which reduces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is
driven low. In powerdown, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing
current supply. To exit Powerdown, TPWDNB must be driven high. When the Serializer exits Powerdown, its PLL
must lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization
before data transfer can begin. The Deserializer enters powerdown mode when RPWDNB is driven low. In
powerdown mode, the PLL stops and the outputs enter TRI-STATE. To bring the Deserializer block out of the
powerdown state, the system drives RPWDNB high.
Both the Serializer and Deserializer must reinitialize and relock before data can be transferred. The Deserializer
will initialize and assert LOCK high when it is locked to the embedded clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN or TPWDNB pin is driven low. This will TRI-STATE both
driver output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer will return to the previous state
as long as all other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the Deserializer enters TRI-STATE. Consequently, the receiver
output pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the
state of the PLL. The Deserializer input pins are high impedance during receiver powerdown (RPWDNB low) and
power-off (V_DD = 0V).
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