DS90UR124Q_14 Datasheet, PDF (27/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
D_OUT+ 100 nF
100 nF R_IN+
100:
100:
D_OUT-
100 nF
100 nF ^RIN^-
Figure 23. AC Coupled Application
1 CLK cycle
*Note: bits [0-23] are not physically located in positions shown above since bits [0-23] are scrambled and DC
Balanced
Figure 24. Single Serialized LVDS Bitstream*
DS90UR241
DS90UR241
0.1 PF
100:
0.1 PF
0.1 PF
50:
4.7 nF
50:
0.1 PF
RIN+
DS90UR124
RIN-
Figure 25. Receiver Termination Option 2
0.1 PF
100:
VDD
0.1 PF
R_PU
50:
R_PD
4.7 nF
50:
0.1 PF
0.1 PF
RIN+
DS90UR124
RIN-
Figure 26. Receiver Termination Option 3
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