DS90UR124Q_14 Datasheet, PDF (26/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
www.ti.com
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Termination of the LVDS interconnect is required. For point-to-point applications, termination should be located at
both ends of the devices. Nominal value is 100 Ohms to match the line’s differential impedance. Place the
resistor as close to the transmitter DOUT± outputs and receiver RIN± inputs as possible to minimize the resulting
stub between the termination resistor and device.
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds
26
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR124Q DS90UR241Q