DS90UR124Q_14 Datasheet, PDF (28/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
Truth Tables
www.ti.com
TPWDNB
(Pin 9)
L
H
H
H
H
DEN
(Pin 18)
X
L
H
H
H
Table 1. DS90UR241 Serializer Truth Table
RAOFF
(Pin 12)
X
X
X
L
H
Tx PLL Status
(Internal)
X
X
Not Locked
Locked
Locked
LVDS Outputs
(Pins 19 and 20)
Hi Z
Hi Z
Hi Z
Serialized Data with Embedded Clock
(DS90UR124 compatible)
Serialized Data with Embedded Clock
(DS90C124 compatible)
RPWDNB
(Pin 48)
L
H
H
H
H
REN
(Pin 60)
X
L
H
H
H
Table 2. DS90UR124 Deserializer Truth Table
RAOFF
(Pin 63)
X
X
Rx PLL Status
(Internal)
X
X
ROUTn and RCLK
(See Pin Diagram)
Hi Z
Hi Z
X
Not Locked
Hi Z
L
Locked
Data and RCLK Active
(DS90UR241 compatible)
H
Locked
Data and RCLK Active
(DS90C241 compatible)
LOCK
(Pin 23)
Hi Z
L = PLL Unocked;
H = PLL Locked
L
H
H
Revision History
• Revision M, October 4, 2011
Updated Applications Information for Transmission Media. Added figure describing Receiver Input Eye
Opening
Changes from Revision M (March 2013) to Revision N
Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 28
28
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