DS90UR124Q_14 Datasheet, PDF (7/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
www.ti.com
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
t_RCP
Receiver out Clock Period
t_RCP = t_TCP,
PTOSEL = H
RCLK
Figure 15⁽¹⁾
23.25
T
t_RDC
RCLK Duty Cycle
PTOSEL = H,
SLEW = L
45
50
t_CLH
LVCMOS Low-to-High
C_L = 4 pF
R_OUT [0:23],
Transition Time
(lumped load), RCLK, LOCK
1.5
t_CHL
LVCMOS High-to-Low
SLEW = H ⁽²⁾⁽¹⁾
Transition Time
1.5
t_CLH
LVCMOS Low-to-High
C_L = 4 pF
R_OUT [0:23],
Transition Time
(lumped load), RCLK, LOCK
2.0
t_CHL
LVCMOS High-to-Low
SLEW = L⁽²⁾⁽¹⁾
Transition Time
2.0
t_ROS
t_ROH
t_ROS
t_ROH
t_ROS
t_ROH
t_ROS
t_ROH
t_ROS
t_ROH
t_ROS
t_ROH
t_HZR
t_LZR
t_ZHR
t_ZLR
t_DD
t_DSR
R_OUT (0:7) Setup Data to
RCLK (Group 1)
R_OUT (0:7) Hold Data to RCLK
(Group 1)
R_OUT (8:15) Setup Data to
RCLK (Group 2)
R_OUT (8:15) Hold Data to
RCLK (Group 2)
R_OUT (16:23) Setup Data to
RCLK (Group 3)
R_OUT (16:23) Setup Data to
RCLK (Group 3)
R_OUT (0:7) Setup Data to
RCLK (Group 1)
R_OUT (0:7) Hold Data to RCLK
(Group 1)
R_OUT (8:15) Setup Data to
RCLK (Group 2)
R_OUT (8:15) Hold Data to
RCLK (Group 2)
R_OUT (16:23) Setup Data to
RCLK (Group 3)
R_OUT (16:23) Setup Data to
RCLK (Group 3)
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay
Deserializer PLL Lock Time
from Powerdown
PTOSEL = L,
SLEW = H,
Figure 16⁽¹⁾
PTOSEL = L,
SLEW = H,
Figure 16⁽¹⁾
PTOSEL = H,
SLEW = H,
Figure 15⁽¹⁾
PTOSEL = H,
Figure 14⁽³⁾
PTOSEL = H,
Figure 12⁽³⁾
See ^{(2) (4)}
RxIN_TOL-L
RxIN_TOL-R
Receiver INput TOLerance
Left
Receiver INput TOLerance
Right
See ^{(2) (5) (6)}
Figure 17
See ^{(2) (5) (6)}
Figure 17
R_OUT[0:7]
R_OUT [8:15],
LOCK
R_OUT [16:23]
R_OUT[0:7]
R_OUT [8:15],
LOCK
R_OUT [16:23]
R_OUT [0:23],
RCLK, LOCK
RCLK
5 MHz
43 MHz
5 MHz–43 MHz
5 MHz–43 MHz
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.5*t_RCP)–3 UI
(0.5*t_RCP)–3 UI
(0.5*t_RCP)–3 UI
(0.5*t_RCP)–3 UI
(0.5*t_RCP)–3 UI
(0.5*t_RCP)–3 UI
(0.5*t_RCP)–2 UI
(0.5*t_RCP)+2 UI
(0.5*t_RCP)−1 UI
(0.5*t_RCP)+1 UI
(0.5*t_RCP)+1 UI
(0.5*t_RCP)–1 UI
3
3
3
3
[5+(5/56)]T+3.7
Max Units
200
ns
55
%
2.5
ns
2.5
ns
3.5
ns
3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
10
ns
10
ns
10
ns
[5+(5/56)]T ns
+8
128k*T ms
128k*T ms
0.25
UI
0.25
UI
(1) Figure 5, Figure 15 and Figure 16 show a rising edge data strobe (TCLK IN/RCLK OUT).
(2) Specification is guaranteed by characterization and is not tested in production.
(3) Figure 1, Figure 2, Figure 8, Figure 12 and Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
(4) t_DSR is the time required by the Deserializer to obtain lock when exiting powerdown mode.
(5) RxIN_TOL is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail.
(6) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
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