DS90UR124Q_14 Datasheet, PDF (8/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
AC Timing Diagrams and Test Circuits
Device Pin Name
Signal Pattern
TCLK
ODD DIN
EVEN DIN
Figure 1. Serializer Input Checkerboard Pattern
Device Pin Name
Signal Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 2. Deserializer Output Checkerboard Pattern
D_OUT+
10 pF
100:
Vdiff
80%
20%
80%
Vdiff = 0V
20%
D_OUT-
10 pF
Vdiff = (D_OUT+) - (D_OUT-)
t_LLHT
t_LHLT
Figure 3. Serializer LVDS Output Load and Transition Times
TCLK
80%
20%
80%
V_DD
20%
0V
t_CLKT
t_CLKT
Figure 4. Serializer Input Clock Transition Times
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