DS90UR124Q_14 Datasheet, PDF (20/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
www.ti.com
PRE-EMPHASIS
The DS90UR241 features a Pre-Emphasis function used to compensate for long or lossy transmission media.
Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output current
during transitions to counteract cable loading effects. The transmission distance will be limited by the loss
characteristics and quality of the media. Pre-Emphasis adds extra current during LVDS logic transition to reduce
the cable loading effects and increase driving distance. In addition, Pre-Emphasis helps provide faster
transitions, increased eye openings, and improved signal integrity. The ability of the DS90UR241 to use the Pre-
Emphasis feature will extend the transmission distance up to 10 meters in most cases.
To enable the Pre-Emphasis function, the “PRE” pin requires one external resistor (Rpre) to Vss in order to set
the additional current level. Values of Rpre should be between 6kΩ and 100MΩ. Values less than 6kΩ should not
be used. A lower input resistor value on the ”PRE” pin increases the magnitude of dynamic current during data
transition. The additional source current is based on the following formula: PRE = (R_PRE ≥ 6kΩ); I_MAX = [48 /
R_PRE]. For example if Rpre = 15kΩ , then the Pre-Emphasis current is increase by an additional 3.2 mA.
The amount of Pre-Emphasis for a given media will depend on the transmission distance of the application. In
general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This can result in
excessive noise, crosstalk and increased power dissipation. For short cables or distances, Pre-Emphasis may
not be required. Signal quality measurements are recommended to determine the proper amount of Pre-
Emphasis for each application.
AC-COUPLING AND TERMINATION
The DS90UR241 and DS90UR124 supports AC-coupled interconnects through integrated DC balanced
encoding/decoding scheme. To use the Serializer and Deserializer in an AC coupled application, insert external
AC coupling capacitors in series in the LVDS signal path as illustrated in Figure 23. The Deserializer input stage
is designed for AC-coupling by providing a built-in AC bias network which sets the internal V_CM to +1.8V. With AC
signal coupling, capacitors provide the ac-coupling path to the signal input.
For the high-speed LVDS transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The most common
used capacitor value for the interface is 100 nF (0.1 uF) capacitor. NPO class 1 or X7R class 2 type capacitors
are recommended. 50 WVDC should be the minimum used for the best system-level ESD performance.
A termination resistor across DOUT± and RIN± is also required for proper operation to be obtained. The
termination resistor should be equal to the differential impedance of the media being driven. This should be in the
range of 90 to 132 Ohms. 100 Ohms is a typical value common used with standard 100 Ohm transmission
media. This resistor is required for control of reflections and also completes the current loop. It should be placed
as close to the Serializer DOUT± outputs and Deserializer RIN± inputs to minimize the stub length from the pins.
To match with the deferential impedance on the transmission line, the LVDS I/O are terminated with 100 Ohm
resistors on Serializer DOUT± outputs pins and Deserializer RIN± input pins.
Receiver Termination Option 1
A single 100 Ohm termination resistor is placed across the RIN± pins (see Figure 23). This provides the signal
termination at the Receiver inputs. Other options may be used to increase noise tolerance.
Receiver Termination Option 2
For additional EMI tolerance, two 50 Ohm resistors may be used in place of the single 100 Ohm resistor. A small
capacitor is tied from the center point of the 50 Ohm resistors to ground (see Figure 25). This provides a high-
frequency low impedance path for noise suppression. Value is not critical, 4.7nF maybe used with general
applications.
Receiver Termination Option 3
For high noise environments an additional voltage divider network may be connected to the center point. This
has the advantage of a providing a DC low-impedance path for noise suppression. Use resistor values in the
range of 100Ω-2KΩ for the pullup and pulldown. Ratio the resistor values to bias the center point at 1.8V. For
example (see Figure 26): V_DD=3.3V, Rpullup=1KΩ, Rpulldown=1.2KΩ; or Rpullup=100Ω, Rpulldown=120Ω
(strongest). The smaller values will consume more bias current, but will provide enhanced noise suppression.
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